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1 ds04-21362-2e fujitsu semiconductor data sheet assp dual serial input pll frequency synthesizer mb15f08sl n description the fujitsu mb15f08sl is a serial input phase locked loop (pll) frequency synthesizer with a 2500 mhz and a 1100 mhz prescalers. the 2500 mhz prescaler, and 1100 mhz prescaler have a dual modulus division ratio of 32/ 33 or 64/65 and 16/17 or 32/33 enabling pulse swallow operation. the supply voltage range is between 2.4 v and 3.6 v. the mb15f08sl uses the latest bicmos process. as a result, the supply current is typically 7.0 ma at 2.7 v. a refined charge pump supplies a well-balanced output current of 1.5 ma or 6 ma. the charge pump current is selectable by serial data. mb15f08sl is ideally suited for wireless mobile communications. n features ? high frequency operation: rx synthesizer: 2500 mhz max tx synthesizer: 1100 mhz max ? low power supply voltage: v cc = 2.4 to 3.6 v ? ultra low power supply current: i cc = 7.0 ma typ. (v cc = 2.7 v, ta = +25 c, in tx, rx locking state) i cc = 7.5 ma typ. (v cc = 3.0 v, ta = +25 c, in tx, rx locking state) ? direct power saving function: power supply current in power saving mode typ. 0.1 m a (v cc = 3v, ta = +25 c), max. 10 m a (v cc = 3v) ? dual modulus prescaler: 2500 mhz prescaler (32/33 or 64/65)/1100 mhz prescaler (16/17 or 32/33) ? serial input 14-bit programmable reference divider: r = 3 to 16,383 ? serial input programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 3 to 2,047 ? software selectable charge pump current ? onCchip phase control for phase comparator ? operating temperature: ta = C40 to +85 c n packages 16-pin, plastic ssop (fpt-16p-m05) 16-pad, plastic bcc (lcc-16p-m04)
2 mb15f08sl n pin assignments gnd rx osc in gnd tx fin tx v cctx ld/fout ps tx d otx clock data le fin rx v ccrx xfin rx ps rx d orx 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 gnd rx clock d otx d orx 1 2 3 4 5 678 9 10 11 12 13 14 15 16 osc in gnd tx fin tx v cctx ps tx ld/fout data le fin rx v ccrx ps rx xfin rx top view top view (fpt-16p-m05) (lcc-16p-m04) 16-pin ssop 16-pad bcc
3 mb15f08sl n pin description pin no. pin name i/o descriptions ssop bcc 116gnd rx C ground for rx-pll section. 21osc in i the programmable reference divider input. tcxo should be connected with a ac coupling capacitor. 32gnd tx C ground for the tx-pll section. 43fin tx i prescaler input pin for the tx-pll. connection to an external vco should be via ac coupling. 54v cctx C power supply voltage input pin for the tx-pll section. 6 5 ld/fout o lock detect signal output (ld)/phase comparator monitoring output (fout). the output signal is selected by lds bit in the serial data. lds bit = h ; outputs fout signal lds bit = l ; outputs ld signal 76ps tx i power saving mode control for the tx-pll section. this pin must be set at l during power-on. (open is prohibited.) ps tx = h ; normal mode ps tx = l ; power saving mode 87do tx o charge pump output for the tx-pll section. phase characteristics of the phase detector can be selected via programming of the fc-bit. 98do rx o charge pump output for the rx-pll section. phase characteristics of the phase detector can be selected via programming of the fc-bit. 10 9 ps rx i power saving mode control for the rx-pll section. this pin must be set at l during power-on. (open is prohibited.) ps rx = h ; normal mode ps rx = l ; power saving mode 11 10 xfin rx i prescaler complementary input for the rx-pll section. this pin should be grounded via a capacitor. 12 11 v ccrx C power supply voltage input pin for the rx-pll section, the shift register and the oscillator input buffer. when power is off, latched data of rx-pll is lost. 13 12 fin rx i prescaler input pin for the rx-pll. connection to an external vco should be via ac coupling. 14 13 le i load enable signal inpunt (with a schmitt trigger input buffer.) when the le bit is set h, data in the shift register is transferred to the corresponding latch according to the control bit in the serial data. 15 14 data i serial data input (with a schmitt trigger input buffer.) a data is transferred to the corresponding latch (tx-ref counter, tx-prog. counter, rx-ref. counter, rx-prog. counter) according to the control bit in the serial data. 16 15 clock i clock input for the 23-bit shift register (with a schmitt trigger input buffer.) one bit of data is shifted into the shift register on a rising edge of the clock.
4 mb15f08sl n block diagram 16 clock 15 data 14 le 10 ps rx 11 xfin rx 13 fin rx osc in fin tx ps tx 3-bit latch 7-bit latch 11-bit latch 3-bit latch latch selector 23-bit shift register 7-bit latch 11-bit latch phase comp. (tx-pll) lock det. (tx-pll) lock det. (rx-pll) charge pump. (tx-pll) current switch phase comp. (rx-pll) charge pump. (rx-pll) current switch 2-bit latch 14-bit latch 1-bit latch 2-bit latch 14-bit latch 1-bit latch intermittent mode control (tx-pll) intermittent mode control (rx-pll) schmitt circuit schmitt circuit schmitt circuit binary 7-bit swallow counter (tx-pll) binary 14-bit programmable ref. counter (tx-pll) c/p setting current binary 11-bit programmable counter (tx-pll) binary 7-bit swallow counter (rx-pll) binary 11-bit programmable counter (rx-pll) prescaler (tx-pll) 16/17, 32/33 prescaler (rx-pll) 32/33, 64/65 fc tx sw tx lds fc rx sw rx lds v cctx gnd tx 5 3 fp tx 8 do tx ld tx selector t1 t2 t1 t2 9 do rx or 6 ld / fout fr rx fp rx fr tx c n 1 c n 2 and ld fr tx fr rx fp tx fp rx v ccrx gnd rx 7 (6) (3) (1) (12) (10) (9) (13) (14) (15) 4 2 (8) (5) (7) (2) (4) binary 14-bit programmable ref. counter (rx-pll) c/p setting current 1-bit latch 12 (11) 1 (16) o -- ssop ( ) -- bcc
5 mb15f08sl n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit remark min. max. power supply voltage v cc C0.5 +4.0 v input voltage v i C0.5 v cc +0.5 v output voltage v o gnd v cc v storage temperature t stg C55 +125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.4 3.0 3.6 v input voltage v i gnd C v cc v operating temperature ta C40 C +85 c
6 mb15f08sl n electrical characteristics (v cc = 2.4 to 3.6 v, ta = C40 to +85 c) (continued) parameter symbol condition value unit min. typ. max. power supply current* 1 i cctx *1 fin tx = 1100 mhz v cctx = 2.7 v C 2.6 Cma (v cctx = 3.0 v) (2.8) i ccrx *1 fin rx = 2500 mhz v ccrx = 2.7 v C 4.4 Cma (v ccrx = 3.0 v) (4.7) power saving current i ps ps tx = ps rx = l C 0.1* 2 10 m a operating frequency fin tx *3 fin tx tx pll 100 C 1100 mhz fin rx *3 fin rx rx pll 400 C 2500 mhz osc in fosc C 3 C 40 mhz input sensitivity fin tx pfin tx tx pll, 50 w system C10 C +2 dbm fin rx *8 pfin rx rx pll, 50 w system C15 C +2 dbm osc in v osc C0.5Cv cc vp-p h level input voltage data, clock, le, v ih schmitt trigger input v cc 0.7 + 0.4 CC v l level input voltage v il schmitt trigger input C C v cc 0.3 C 0.4 h level input voltage ps v ih Cv cc 0.7 C C v l level input voltage v il CCCv cc 0.3 h level input current data, clock, le, ps i ih *4 CC1.0C+1.0 m a l level input current i il *4 CC1.0C+1.0 h level input current osc in i ih C 0 C +100 m a l level input current i il *4 CC100C0 h level output voltage ld/fout v oh v cc = 3 v, i oh = C1 ma v cc C 0.4 C C v l level output voltage v ol v cc = 3 v, i ol = 1 ma C C 0.4 h level output voltage do tx do rx v doh v cc = 3 v, i doh = C0.5 ma v cc C 0.4 C C v l level output voltage v dol v cc = 3 v, i dol = 0.5 ma C C 0.4 high impedance cutoff current do tx do rx i off v cc = 3 v, v off = 0.5 v to v cc C0.5v CC2.5na h level output current ld/fout i oh *4 v cc = 3 v C C C1.0 ma l level output current i dol *4 v cc = 3 v 1.0 C C h level output current do tx do rx i doh *4 v cc = 3 v, v doh = v cc /2, ta = + 2 5 c cs bit = h C C6.0 C ma cs bit = l C C1.5 C
7 mb15f08sl (continued) (v cc = 2.4 to 3.6 v, ta = C40 to +85 c) *1: conditions; fosc = 12 mhz, ta = +25 c, sw=l, in locking state. *2: v cctx = v ccrx = 3.0 v, fosc = 12.8 mhz, ta = +25 c, in power saving state. *3: ac coupling. 1000pf capacitor is connected under the condition of min. operating frequency. *4: the symbol C (minus) means direction of current flow. *5: v cc = 3.0 v, ta = +25 c (|i 3 | C |i 4 |)/[(|i 3 | + |i 4 |)/2] 100(%) *6: v cc = 3.0 v, ta = +25 c [(|i 2 | C |i 1 |)/2]/[(|i 1 | + |i 2 |)/2] 100(%) (applied to each i dol , i doh ) *7: v cc = 3.0 v, [|i do(85 c) C i do(C40 c) |/2]/[|i do(85 c) + i do(C40 c) |/2] 100(%) (applied to each i dol , i doh ) *8: fin operating frequency input sensitivity(min.) 400 mhz fin 2200 mhz C15 dbm 2200 mhz < fin 2500 mhz C10 dbm parameter symbol condition value unit min. typ. max. l level output current do tx do rx i dol v cc = 3 v, v dol = v cc /2, ta = + 2 5 c cs bit = h C 6.0 C ma cs bit = l C 1.5 C charge pump current rate i dol /i doh i domt *5 v do = v cc /2 C3C% vs v do i dovd *6 0.5 v v do v cc C 0.5 v C 10 C % vs ta i dota *7 C40 c ta + 85 c, v do = v cc /2 C10C% i 1 i 1 i 3 i 2 i 2 i 4 i dol i doh 0.5 v cc / 2v cc v cc - 0.5 v charge pump output voltage (v)
8 mb15f08sl n functional description the divide ratio can be calculated using the following equation: f vco = [(m n) + a] f osc ? r (a < n) f vco : output frequency of external voltage controlled oscillator (vco) m : preset divide ratio of dual modulus prescaler (16or 32 for tx-pll, 32 or 64 for rx-pll) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : reference oscillation frequency r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of tx/rx-pll sections, programmable reference dividers of tx/rx-pll sections are controlled individually. serial data of binary data is entered through data pin. on rising edge of clock, one bit of serial data is transferred into the shift register. when the le signal is taken high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. table.1 control bit shift register configuration control bit destination of serial data cn1 cn2 l l the programmable reference counter for the tx-pll h l the programmable reference counter for the rx-pll l h the programmable counter and the swallow counter for the tx-pll h h the programmable counter and the swallow counter for the rx-pll programmable reference counter msb data flow cn1,2 : control bit [table. 1] r1 to r14 : divide ratio setting bit for the programmable reference counter (5 to 16,383)[table. 2] t1, 2 : test purpose bit [table. 3] cs : charge pump currnet select bit [table. 9] x : dummy bits (set 0 or 1) note : data input with msb first. 1234567891011121314151617181920212223 c n 1 c n 2 t 1 t 2 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 c s xxxx lsb
9 mb15f08sl table2. binary 14-bit programmable reference counter data setting note: divide ratio less than 3 is prohibited. table.3 test purpose bit setting divide ratio (r) r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 3 00000000000011 4 00000000000100 16383 11111111111111 t 1 t 2 ld/fout pin state l l outputs fr tx h l outputs fr rx l h outputs fp tx h h outputs fp rx programmable counter lsb msb data flow cnt1, 2 : control bit [table. 1] n1 to n11: divide ratio setting bits for the programmable counter (3 to 2,047) [table. 4] a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) [table. 5] sw tx/rx : divide ratio setting bits for the prescaler [table. 6] (16/17 or 32/33 for the sw tx , 32/33 or 64/65 for the sw rx ) fc tx/rx : phase control bit for the phase detector (tx: fc tx , rx: fc rx )[table. 7] lds : ld/fout signal select bit [table. 8] note: data input with msb first. 1 2 3 4 5 6 7 8 9 1011121314151617181920212223 c n 1 c n 2 l d s s w tx/ rx f c tx/ rx a 1 a 2 a 3 a 4 a 5 a 6 a 7 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n 11
10 mb15f08sl table.4 brinary 11-bit programmable counter data setting note: divide ratio less than 3 is prohibited. table.5 brinary 7-bit swallow counter data setting note: divide ratio (a) range = 0 to 127 table.6 prescaler data setting table.7 phase comparator phase switching data setting note: z = high-impedance depending upon the vco and lpf polarity, fc bit should be set. table.8 ld/fout output select data setting divide ratio (n) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 3 00000000011 4 00000000100 2047 1 1 1 1 1 1 1 1 1 1 1 divide ratio (n) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 127 1111111 sw = h sw = l prescaler divide ratio tx-pll 16/17 32/33 rx-pll 32/33 64/65 fc tx, rx = h fc tx, rx = l do tx, rx fr > fp h l fr = fp z z fr < fp l h vco polarity (1) (2) lds ld/fout output signal hfout (fr tx, rx , fp tx, rx ) signals l ld signal (1) (2) lpf output voltage vco output frequency
11 mb15f08sl table.9 charge pump current setting power saving mode (intermittent mode control circuit) table.10 ps pin setting the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pin high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. note: when power (v cc ) is first applied, the device must be in standby mode, ps = low, for at least 1 m s. note: ps pin must be set l for power-on . cs current value h 6.0 ma l 1.5 ma ps pin status h normal mode l power saving mode on off v cc clock data le ps (1) (2) (3) t v 3 1 m s tps 3 100 ns (1) ps = l (power saving mode) at power-on (2) set serial data 1 m s later after power supply remains stable (vcc > 2.2 v). (3) release power saving mode (ps : l ? h) 100 ns later after setting serial data.
12 mb15f08sl n serial data input timing lsb msb clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 1st data 2nd data control bit invalid data on rising edge of the clock, one bit of the data is transferred into the shift register. parameter unit max. typ. min. t1 t2 t3 t4 ns ns ns ns 20 C C C C C C C C 20 30 30 100 C C C C C C 20 100 t5 t6 t7 ns ns ns parameter unit max. typ. min. note: le should be l when the data is transferred into the shift register.
13 mb15f08sl n phase comparator output waveform notes: phase error detection range = C2 p to +2 p pulses on do tx/rx signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on oscin input frequency as follows. t wu > 2/fosc: i. e. t wu > 156.3 ns when foscin = 12.8 mhz t wu < 4/fosc: i. e. t wl < 312.5 ns when foscin = 12.8 mhz fr tx / rx fp tx / rx ld d otx / rx t wu t wl d otx / rx h l (fc bit = high) (fc bit = low) z z ld output logic table tx-pll section rx-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l
14 mb15f08sl n measurment circuit (for measuring input sensitivity fin/oscin) s g s g 50 w 1000 pf 0.1 m f 50 w 1000 pf v cctx fout 50 w 1000 pf 1000 pf s g 0.1 m f v ccrx 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 d otx ps tx ld / fout v cctx fin tx gnd tx osc in gnd rx gnd d orx ps rx xfin rx v ccrx fin rx le data clock controller (divide ratio setting) mb15f08sl oscilloscope note: ssop-16
15 mb15f08sl n typical characteristics 1. fin input sensitivity rx pll input sensitivity - input frequency input frequency fin rx (mhz) input sensitivity pfin rx (dbm) tx pll input sensitivity - input frequency input sensitivity pfin tx (dbm) input frequency fin tx (mhz) 10 5 0 - 5 - 20 - 15 - 10 - 25 - 35 - 30 - 40 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec 10 5 0 - 5 - 20 - 15 - 10 - 25 - 35 - 30 - 40 0 200 400 600 800 1000 1200 1400 1600 ta = +25 c ta = +25 c v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec
16 mb15f08sl 2. osc in input sensitivity input sensitivity - input frequency input frequency f osc (mhz) input sensitivity v osc (dbm) 10 0 - 20 - 30 - 40 - 10 - 50 0 40 60 80 100 20 140 160 180 220 120 200 240 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = +25 c spec
17 mb15f08sl 3. do output current (rx pll) i do - v do i do - v do charge pump output voltage v do (v) charge pump output current i do (ma) charge pump output voltage v do (v) charge pump output current i do (ma) 10.00 - 10.00 0 .6000/div 4.800 2.000 /div 0 ta = +25 c v cc = 3.0 v i doh i dol 10.00 - 10.00 0 .6000/div 4.800 2.000 /div 0 ta = +25 c v cc = 3.0 v i doh i dol 1.5 ma mode 6.0 ma mode
18 mb15f08sl 4. do output current (tx pll) i do - v do i do - v do charge pump output voltage v do (v) change pump output current i do (ma) charge pump output voltage v do (v) charge pump output current i do (ma) 10.00 - 10.00 0 .6000/div 4.800 2.000 /div 0 ta = +25 c v cc = 3.0 v i doh i dol 10.00 - 10.00 0 .6000 / div 4.800 2.000 /div 0 ta = +25 c v cc = 3.0 v i doh i dol 1.5 ma mode 6.0 ma mode
19 mb15f08sl 5. fin input impedance fin tx input impedance 382.09 w - 720 w 100 mhz 32.828 w - 218.91 w 400 mhz 11.242 w - 97.672 w 800 mhz 1 : 2 : 3 : start 100.000 000 mhz stop 1 200.000 000 mhz 4 : 9.4512 w - 50.598 w 1200 mhz 1 2 3 4 fin rx input impedance 393.91 w - 714.91 w 100 mhz 9.5156 w - 69.926 w 1 ghz 27.894 w - 13.635 w 2 ghz 1 : 2 : 3 : start 100.000 000 mhz stop 2 500.000 000 mhz 4 : 18.047 w - 1.2236 w 2.5 ghz 1 2 3 4
20 mb15f08sl 6. osc in input impedance osc in input impedance 8.8755 k w - 2.52 k w 3 mhz 4.796 k w - 4.934 k w 10 mhz 1.7043 k w - 3.8729 k w 20 mhz 1 : 2 : 3 : start 3.000 000 mhz stop 40.000 000 mhz 4 : 439.87 w - 2.1714 k w 40 mhz 2 3 4 1
21 mb15f08sl n reference information s.g spectrum analyzer osc in fin do lpf vco test circuit f vco = 1733 mhz k v = 44 mhz / v fr = 200 khz f osc = 13 mhz v cc = 3.0 v v vco = 3.5 v ta = + 25 c cp : 6 ma mode 27 k w 1.9 k w 0.022 m f 200 pf 2200 pf lpf atten center span 1.000 mhz 1.733000 ghz rbw 3.0 khz swp vbw 3.0 khz 280 ms d mkr - 79.83 db 10 db rl 200 khz 0 dbm 10 dbm / atten center span 50.00 khz 1.73300000 ghz rbw 300 hz swp vbw 300 hz 1.40 sec d mkr - 48.67 db 10 db rl 14.25 khz 0 dbm 10 db / 73.4 dbc / hz 15.5 khz pll reference leakage pll phase noise
22 mb15f08sl (continued) 1.90300 ghz 1.80300 ghz 1.70300 ghz - 678 m s 1.822 ms 500.0 m s / div 4.322 ms t 1 400 m st 2 867 m s d 467 m s 1.83300 ghz 1.73300 ghz 1.63300 ghz - 678 m s 1.822 ms 500.0 m s / div 4.322 ms t 1 400 m st 2 867 m s d 467 m s - 678 m s 1.822 ms 500.0 m s / div 4.322 ms t 1 400 m st 2 889 m s d 489 m s - 678 m s 1.822 ms 500.0 m s / div 4.322 ms t 1 400 m st 2 867 m s d 467 m s 1.733004750 ghz 1.733000750 ghz 1.732996750 ghz 1.803005000 ghz 1.803001000 ghz 1.802997000 ghz pll lock up time pll lock up time 1733 mhz ? 1803 mhz within 1 khz lch ? hch 467 m s 1803 mhz ? 1733 mhz within 1 khz hch ? lch 467 m s
23 mb15f08sl n application example n usage precautions (1) vcc rx must equa vcc tx . even if either rx-pll or tx-pll is not used, power must be supplied to both v ccrx and v cctx to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect damage by electrostatic discharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -tum off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. 1000 pf 0.1 m f 12345678 16 15 14 13 12 11 10 9 1000 pf output 3 v mb15f08sl 1000 pf 1000 pf 3 v 0.1 m f output lockdet vco lpf vco lpf tcxo do rx ps rx xfin rx v ccrx fin rx le data clock do tx ps tx ld / fout v cctx fin tx gnd tx osc in gnd rx note: ssop-16 from a controller
24 mb15f08sl n ordering information part number package remarks mb15f08slpfv1 16-pin, plastic ssop (fpt-16p-m05) MB15F08SLPV1 16-pad, plastic bcc (lcc-16p-m04)
25 mb15f08sl n package dimensions (continued) c 1994 fujitsu limited f16013s-2c-4 0.50?.20 (.020?008) 0.10?.10(.004?004) (stand off) 0 10 details of "a" part 4.55(.179)ref 5.00?.10(.197?004) * 0.65?.12 5.40(.213) 4.40?.10 6.40?.20 nom (.252?008) (.173?004) * (.0256?0047) .006 ?001 +.002 ?.02 +0.05 0.15 .009 ?002 +.004 ?.05 +0.10 0.22 .049 ?004 +.008 ?.10 +0.20 1.25 0.10(.004) "a" index (mounting height) dimensions in mm (inches ) 16-pin, plastic ssop (fpt-16p-m05) * : these dimensions do not include resin protrusion.
26 mb15f08sl (continued) c 1999 fujitsu limited c16015s-1c-1 0.325?.10 (.013?004) 3.40(.134)typ "a" 0.40?.10 (.016?004) 3.25(.128) 0.80(.031) ref typ 4.20?.10 (.165?004) 4.55?.10 (.179?004) 0.80(.031)max mounting height 0.075?.025 (.003?001) (stand off) 0.05(.002) 6 9 1 14 9 14 1 6 0.40?.10 (.016?004) 0.75?.10 (.030?004) details of "a" part 1.725(.068) ref 1.55(.061) ref "b" details of "b" part (.024?004) 0.60?.10 (.024?004) 0.60?.10 0.65(.026) typ index area dimensions in mm (inches) 16-pad, plastic bcc (lcc-16p-m04)
27 mb15f08sl fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9904 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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